Flash EPROMS are non-volatile electrically erasable integrated circuit memory devices. Flash EPROMS utilize hot-electron injection for programming and Fowler-Nordheim tunnelling for erase. A cross-section of a conventional flash EPROM is illustrated in FIG. 1. The flash memory cell 10 is typically fabricated in a substrate 20 of p-type silicon with a source region 14 optimized for the erase condition and a drain region 16 optimized for hot-electron programming. The flash memory cell 10 also includes a floating gate 18 and a control gate 12, separated by a thin dielectric 22.
In flash EPROMS, the floating gate 18 is typically programmed by channel hot-electron injection, and erased by Fowler-Nordheim tunnelling. Capacitive coupling, in these stacked gate structures, to the control gate 12, creates the field across the floating gate 18 necessary to accumulate the electrons. In order to maximize the capacitive coupling between the control gate 12 and the floating gate 18, the dielectric 22 separating the two is fabricated with as thin a layer as is possible, and from a material having a high dielectric constant. It is known in the prior art to pattern polysilicon to form the floating gate 18. The dielectric 22 is then formed by creating an insulation film on the floating gate 18. This insulation film is typically created by thermally growing silicon oxide, depositing silicon nitride, and then re-oxidizing the silicon nitride to create an oxidized-nitride-oxide (ONO) layer. Because the control gate 12 and the floating gate 18 are typically patterned from polysilicon, this dielectric layer 22 is often referred to as the inter-poly dielectric. Similarly, a thin dielectric layer 24 referred to as tunnel oxide, exists between the floating gate 18 and the substrate 20.
Generally, local oxidation of silicon (LOCOS) isolation techniques are used during the fabrication of flash EPROM memory cells. The LOCOS isolation technique is optimal for the isolation of flash EPROM cells due to its high reliability and the high internal voltage levels required by flash EPROM cells. FIG. 2 illustrates a cross section of the substrate 20 after a LOCOS isolation step is performed. During this LOCOS isolation step, field oxide regions 25 are formed in the substrate 20, separated by a thin layer of sacrificial oxide 26. The active regions are established by a subsequent ion implantation step through the sacrificial oxide 26 and are used to establish the threshold voltage of the cell. The isolation process is designed to achieve an acceptable field threshold voltage to route high voltages in the periphery, and field oxide thickness that gives rise to high coupling coefficients.
One major limitation of LOCOS isolation techniques is the problem of active area encroachment which occurs during the growth of the field oxide regions 25. As shown in FIG. 2, during the period of exposure to the oxidizing ambient, areas of the field oxide regions 25 encroach along the edges, thereby forming a bird's beak shaped transition region 28 of SiO2 around the edges of the field oxide regions 25. This area is not flat and, accordingly, cannot be used effectively for active devices or isolation. Accordingly, the size of useable regions on the substrate 20 is decreased by the LOCOS isolation process. Furthermore, the LOCOS isolation technique requires a larger amount of space for device packing compared to other isolation techniques.
Present static random access memory (SRAM) devices typically use shallow trench isolation (STI) techniques. This is due to the fact that SRAMs do not require voltage levels as high and endurance requirements as stringent as flash EPROM devices. STI techniques have a drawback of not being compatible with higher voltages and endurance requirements. However, the STI technique is optimal for the isolation of SRAM cells because it eliminates planarity concerns and multidimensional oxidation effects, such as the bird's beak formed by the LOCOS isolation techniques, thereby allowing smaller dimensional scaling.
FIG. 3 illustrates a cross section of a substrate 30 after a STI step is performed. The STI technique uses trenches 32 etched into the surface of the substrate 30 at the isolation locations, which are subsequently filled with a thermal or deposited oxide. Such trench isolation can provide isolation oxides which extend into the substrate with little or no encroachment.
Flash EPROM and SRAM devices are currently being implemented together within systems and devices. When implemented together, because of the different isolation needs described above, the SRAM device and the flash EPROM are typically manufactured as separate components and then stacked or piggybacked within a package or the system. If the SRAM device and the flash EPROM are implemented separately and piggybacked, then signals sent between the SRAM device and the flash EPROM must exit the originating device and enter the receiving device, leading to possible signal delays. Stacking flash EPROM and SRAM devices within a package may also cause package reliability problems.
Accordingly, what is needed is a method for integrating SRAM and flash EPROM cells within a single device.